Methods of forming shallow trench isolation structures in semiconductor devices

ABSTRACT

Methods of forming a shallow trench isolation structures in semiconductor devices are disclosed. A disclosed method comprises forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate; forming a trench defining first and second active areas by etching the second oxide layer, the nitride layer, the first oxide layer, and the substrate in a predetermined area; forming a third oxide layer along an inside of the trench; forming a fourth oxide layer to fill up the trench; forming a sacrificial oxide layer on the fourth oxide layer; and removing the sacrificial oxide layer, the fourth oxide layer, the third oxide layer, the second oxide layer, and the nitride layer so as to form the shallow trench isolation. Thus, it is possible to minimize the damage of a narrow active area when forming an element isolation area through an STI process.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/181,607, filed Jul. 13, 2005 (Attorney Docket No.OPP-GZ-2007-0230-US-00), and claims the benefit of Korean PatentApplication No. 10-2004-54327, filed Jul. 13, 2004, which areincorporated herein by reference in their entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to semiconductor fabrication,and, more particularly, to methods of forming shallow trench isolationstructures in semiconductor devices.

BACKGROUND

A shallow trench isolation (STI) process for forming an elementisolation region is easier than a local oxidation of silicon (LOCOS)process due to the miniaturization of semiconductor devices.

Conventionally, the STI (Shallow Trench Isolation) process proceeds asfollows. First, a trench is formed by dry-etching a semiconductorsubstrate. The damage caused by dry-etching is curied. Then an oxidelayer is formed inside of the trench by thermal oxidization in order toimprove surface properties, and to achieve a rounding profile of an edgebetween an active area and an isolation area.

Next, an oxide layer is thickly deposited on the entire surface of thesubstrate to fill up the trench (a lining oxide is formed in the trenchin advance of this filling). Then, the semiconductor substrate isplanarized by chemical mechanical polishing.

Depending on the degree of integration of the semiconductor device beingfabricated, an active area defined by the shallow trench isolationstructure includes a narrow active area and a wide active area. Theoxide is more thickly formed on the wide active area than on the narrowactive area.

Therefore, a further process is performed between forming the oxidelayers on the narrow active area and the wide active area. If a chemicalmechanical polishing process is performed with focus on the wide activearea, peeling damage occurs in the narrow active area. This damagedeteriorates the performance and reliability of the fabricatedsemiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an example shallow trench isolationstructure in a semiconductor device fabricated by an example methodperformed in accordance with the teachings of the present invention.

FIGS. 2 a, 2 b, and 2 c are cross-sectional views of an example shallowtrench isolation structure in a semiconductor device, illustrating insequential order an example method performed in accordance with theteachings of the present invention.

FIGS. 3 a, 3 b, 3 c, and 3 d are cross-sectional views of anotherexample shallow trench isolation structure in a semiconductor,illustrating in sequential order another example method performed inaccordance with the teachings of the present invention.

To clarify multiple layers and regions, the thickness of the layers areenlarged in the drawings. Wherever possible, the same reference numberswill be used throughout the drawing(s) and accompanying writtendescription to refer to the same or like parts. As used in this patent,stating that any part (e.g., a layer, film, area, or plate) is in anyway positioned on (e.g., positioned on, located on, disposed on, orformed on, etc.) another part, means that the referenced part is eitherin contact with the other part, or that the referenced part is above theother part with one or more intermediate part(s) located therebetween.Stating that any part is in contact with another part means that thereis no intermediate part between the two parts.

DETAILED DESCRIPTION Example 1

FIG. 1 is a cross-sectional view of an example shallow trench isolationstructure in a semiconductor device manufactured by an example methodperformed pursuant to the teachings of the present invention.

In the example of FIG. 1, a first oxide layer 102 is formed on asubstrate 100. In addition, an element isolation region defining anactive region is formed in a predetermined area of the first oxide layer102 and the substrate 100. In an element isolation region C, a thirdoxide layer 108 and a fourth oxide layer 110 are formed respectively. Anactive region defined by the element isolation region C is divided intofirst and second regions A and B, whose widths depend on the size of theelement isolation region C. In the illustrated example, the first regionA is wider than the second region B.

An example method of forming the element isolation region is describedin detailed with reference to the enclosed FIGS. 2 a, 2 b, 2 c, and 2 d.

As shown in FIG. 2 a, a first oxide layer 102, a nitride layer 104, anda second oxide layer 106 are sequentially formed on a substrate 100. Aphotoresist pattern PR is formed on the second oxide layer 106. Whileusing the photoresist pattern PR as a mask, a trench T1 is formed byetching the second oxide 106, the nitride layer 104, and the first oxidelayer 102 until the substrate 100 is exposed. In the illustratedexample, the photoresist pattern PR is formed to define first and secondactive regions A and B, and an element isolation region. The sizes ofthe active regions depend on the size of the semiconductor element to beformed thereon. In the illustrated example, the first active region A iswider than the second active region B.

As shown in FIG. 2 b, after the photoresist pattern PR is removed, asecond trench T2 is formed by etching the exposed substrate 100 whileusing the second oxide layer 106 as a mask.

As shown in FIG. 2 c, a third oxide layer 108 is formed on the entiresurface of the substrate 100 and inside of the second trench T2. In theillustrated example, the third oxide layer 108 is formed of a TEOS(Tetra Ethyl Ortho Silicate) layer by performing a LPCVD (Low PressureChemical Vapor Deposition) method. In the illustrated example, the thirdoxide layer 108 is formed to have a thickness of about 10˜200 Å. Next,the second trench T2 is filled with a fourth oxide layer 110 byperforming an HDPCVD (High Density Plasma Chemical Vapor Deposition)method.

In order to form a sacrificial layer for a subsequent chemicalmechanical polishing process, a sacrificial oxide layer 112 is formed onthe substrate 100 by a SOG (Spin On Glass) method. A heat treatment isthen carried out. The heat treatment is performed in an oxygenatmosphere at a high temperature over about 1,000° C. so that impuritieson the surfaces of the sacrificial oxide layer 112 and the fourth oxidelayer 110 are oxidized and removed.

As a result of forming the sacrificial oxide layer 112, the elementisolation region adjacent the narrow active region B can be protectedfrom damage because the narrow active region B is covered and the stepbetween the narrow active region B and the wide active region A isminimized during a chemical mechanical polishing process. Thereliability of the fabricated semiconductor device is improved becausethe heat treatment is performed after forming the sacrificial oxidelayer for removal of the impurities.

Next, as shown in FIG. 1, the sacrificial oxide layer 112, the fourthoxide layer 110, the third oxide layer 108 and the second oxide layer106 are removed by blank etching so that the nitride layer 104 isexposed. Next, the nitride layer 104 is chemically and mechanicallypolished until the first oxide layer 102 is exposed so that thesubstrate 100 is planarized. Residues of the nitride layer 104 can beremoved with phosphoric acid (H₃PO₄).

Example 2

A semiconductor device manufactured by a second example method performedin accordance with the teachings of the present invention has generallythe same resultant structure as a semiconductor device fabricated by thefirst example method described above. However, the second example methodis different from the first example method. The second example methodwill now be described in detailed with reference to FIGS. 3 a, 3 b, 3 cand 3 d.

FIGS. 3 a, 3 b, 3 c and 3 d are cross-sectional views of shallow trenchisolation structures in a semiconductor device manufactured by thesecond example method. As shown in FIG. 3 a, a first oxide layer 102, anitride layer 104, and a second oxide layer 106 are sequentially formedon a substrate 100. A photoresist pattern PR is formed on the secondoxide layer 106. While using the photoresist pattern PR as a mask, thesecond oxide layer 106, the nitride layer 104, and the first oxide layer102 are etched until the substrate 100 is exposed, so that a firsttrench T1 is formed. The sizes of the active regions depend on the sizeof a semiconductor element to be formed thereon. In the illustratedexample, a first active region A is defined to be broader than a secondactive region B.

In the example of FIG. 3 b, after the photoresist pattern PR is removed,a second trench is formed by etching the exposed substrate 100 whileusing the second oxide layer 106 as a mask. This second trenchrepresents a similar area as the trench T2 of the first example shown inFIG. 2 b.

A third oxide layer 108 is formed on the entire surface of the substrate100 and inside the second trench. The third oxide layer 108 is formed ofa TEOS (Tetra Ethyl Ortho Silicate) layer by performing a LPCVD (LowPressure Chemical Vapor Deposition) method. The third oxide layer 108 isformed to have a thickness of about 10˜200 Å. In addition, a fourthoxide layer 110 is formed by an HDPCVD (High Density Plasma ChemicalVapor Deposition) method to fill up the inside of the second trench. Aphotoresist pattern (PR) is then formed on the fourth oxide layer 110 inan area corresponding to the first active region A.

Next, as shown in FIG. 3 c, in order to form a sacrificial layer for achemical mechanical polishing (CMP) process, a sacrificial oxide layer120 is formed over the entire surface of the substrate 100 performing aPECVD (Plasma Enhanced Chemical Vapor Deposition) at a low temperatureof about 180˜220° C. In the illustrated example, the sacrificial oxidelayer 120 is formed by injecting the gases of SiH₄ and O₂, or the gasesof TEOS and O₂ into the PECVD equipment. In consideration of the surfaceproperties, the sacrificial oxide layer 120 can be thinly formed on thephotoresist pattern PR in comparison with the other area.

As shown is FIG. 3 d, the photoresist pattern PR is removed with analkaline solution so that the sacrificial oxide layer 120 remains onlyon the second active area B to continue to protect the second activearea B.

As a result of further forming the sacrificial oxide layer 120, theelement isolation region adjacent to the narrow active region B isprotected from damage and the step between the narrow active region Band the wide active region A is minimized during a subsequent chemicalmechanical polishing process.

Next, as shown in FIG. 1, the sacrificial oxide layer 120, the fourthoxide layer 110, the third oxide layer 108 and the second oxide layer106 are removed so that the nitride layer 104 is exposed. Subsequently,the nitride layer 104 is chemically and mechanically polished until thefirst oxide layer 102 is exposed so that the entire structure isplanarized. In addition, residues of the nitride layer 104 can beremoved with phosphoric acid (H₃PO₄).

From the above description, persons of ordinary skill in the art willappreciate that high quality semiconductor devices have been providedwherein an element isolation region formed around a narrow active areacan be protected by further forming a sacrificial oxide layer.

Persons of ordinary skill in the art will further appreciate thatmethods of forming shallow trench isolation structures in semiconductordevices which are capable of minimizing the damage of a narrow activearea when forming an element isolation area through an STI process havebeen provided.

A disclosed example method of forming a shallow trench isolationstructure in a semiconductor device comprises: forming a first oxidelayer, a nitride layer, and a second oxide layer on a substrate; forminga trench defining first and second active areas by etching the secondoxide layer, the nitride layer, the first oxide layer, and the substratein a predetermined area; forming a third oxide layer inside of thetrench; forming a fourth oxide layer filling the trench; forming asacrificial oxide layer on the fourth oxide layer; and removing thesacrificial oxide layer, the fourth oxide layer, the third oxide layer,the second oxide layer, and the nitride layer to form the shallow trenchisolation structure.

Another example method of forming a shallow trench isolation structurein a semiconductor device comprises: forming a first oxide layer, anitride layer, and a second oxide layer on a substrate; forming a trenchdefining first and second active areas by etching the second oxidelayer, the nitride layer, the first oxide layer, and the substrate in apredetermined area; forming a third oxide layer along an inside of thetrench; forming a fourth oxide layer to fill up the trench; forming aphotoresist pattern on the fourth oxide layer in an area correspondingwith the first active area; forming a sacrificial oxide layer over anentire surface of the substrate and on the photoresist pattern; removingthe photoresist pattern, the sacrificial oxide layer, the fourth oxidelayer, the third oxide layer, the second oxide layer, and the nitridelayer to form the shallow trench isolation.

The sacrificial oxide is preferable formed by a SOG (Spin On Glass)method. In an illustrated example, a heat treatment is performed afterthe sacrificial oxide is formed. The heat treatment is performed in anoxygen atmosphere, and at a temperature over about 1,000° C.

In addition, the sacrificial oxide is preferably formed by a PECVD(Plasma Enhanced Chemical Vapor Deposition) method.

In addition, the third oxide layer is preferably formed to have athickness of about 10˜100 Å.

In addition, the sacrificial oxide layer, the second oxide layer, thethird oxide layer, and the fourth oxide layer are preferably removed bya blanket etching process.

In addition, the nitride layer is preferably removed by a chemicalmechanical polishing process.

In an illustrated example, an etching process is performed usingphosphohydric acid (H₃PO₄) after the chemical mechanical polishingprocess.

Although certain example methods, apparatus and articles of manufacturehave been described herein, the scope of coverage of this patent is notlimited thereto. On the contrary, this patent covers all methods,apparatus and articles of manufacture fairly falling within the scope ofthe appended claims either literally or under the doctrine ofequivalents.

1. A method of forming a shallow trench isolation structure in asemiconductor device comprising: forming a first oxide layer, a nitridelayer, and a second oxide layer above a substrate; forming a secondoxide layer pattern, a nitride layer pattern, and a first oxide layerpattern to expose a shallow trench isolation region in the substrate byetching the second oxide layer, the nitride layer, and the first oxidelayer; forming a trench in the substrate by etching the shallow trenchisolation region using the second oxide layer pattern as a mask; forminga third oxide layer on a wall of the trench; forming a fourth oxidelayer on the substrate to fill the trench; forming a sacrificial oxidelayer on the fourth oxide layer; removing the sacrificial oxide layer,the fourth oxide layer, the third oxide layer pattern, and the secondoxide layer pattern until the nitride layer pattern is exposed; andremoving the nitride layer pattern by a chemical mechanical polishingprocess.
 2. A method as defined in claim 1, wherein the sacrificialoxide layer is formed by an SOG (Spin on Glass) method.
 3. A method asdefined in claim 2, further comprising performing a heat treatment in anoxygen atmosphere at a temperature over about 1,000° C., after formingthe sacrificial oxide layer.
 4. A method as defined in claim 1, whereinthe third oxide layer has a thickness of about 10˜100 Å.
 5. A method asdefined in claim 1, wherein the sacrificial oxide layer, portions of thefourth oxide layer, portions of the third oxide layer, and the secondoxide layer are removed by blanket etching.
 6. A method as defined inclaim 1, further comprising an etching process to remove a nitrideresidue using a phosphoric acid (H₃PO₄) after performing the chemicalmechanical polishing process.
 7. A method as defined in claim 1, furthercomprising forming a first photoresist pattern over the second oxidelayer to define the shallow trench isolation region.
 8. A method asdefined in claim 7, further comprising removing the photoresist patternprior to etching the substrate in the shallow trench isolation region.9. A method as defined in claim 1, wherein forming the third oxide layercomprises low pressure chemical vapor deposition of a TEOS layer.
 10. Amethod as defined in claim 1, wherein filling the trench with the fourthoxide layer comprises high density plasma chemical vapor deposition ofan oxide layer.
 11. A method as defined in claim 7, wherein the firstphotoresist pattern also defines first and second active regions.
 12. Amethod as defined in claim 11, wherein the first active region has agreater width than the second active region.
 13. A method as defined inclaim 1, wherein an upper surface of the fourth oxide layer issubstantially coplanar with the upper surface of the first oxide layer.14. A method as defined in claim 1, wherein removing the nitride layerpattern exposes an upper surface of the first oxide layer.